1. Field of the Invention
Embodiments disclosed herein generally relate to switches that utilize micro-electromechanical systems (MEMS).
2. Description of the Related Art
Currently, MEMS-based non-volatile memory (NVM) design requires all peripheral circuits and the pass gate in each memory cell to be a complementary metal oxide semiconductor (CMOS) device. To further utilize the advantage of MEMS-based design between interconnect layers, one needs to be able to do all of the simple logics with MEMS-only design. At the very end, there will be the interface design between MEMS design and CMOS design. To date, MEMS-only design has not been achieved for NVM devices.
One example of a NVM device is a non-volatile static random access memory (nvSRAM). Many nvSRAM applications comprise fast unlimited as well as random read and write accesses to memory while also having protection against data loss during power failures. Such applications utilize SRAM functionality, but with non-volatile behavior. According to Web-Feet Research (April 2007) the nvSRAM market should grow at 28% CAGR to $956 million in 2012.
Today the nvSRAM market consists of three different approaches. The first approach utilizes existing non-volatile memory without SRAM, such as standard flash, electrically erasable programmable read only memory (EEPROM), flash random access memory (FRAM) and magnetoresistive random access memory (MRAM). These technologies all have limitations with respect to speed and/or endurance.
The second approach is standard SRAM memories with battery backup. However, relying on a battery is not a real fail-safe option and regular replacements of batteries is required and expensive. The third approach is standard SRAM cell architecture, but every memory cell also contains an EEPROM cell (called nvSRAM). nvSRAM can store the data at power failure and restore it at power up. Storing and restoring can also be controlled by the user. However, the memory cells are very large (i.e., about twice the size of a normal SRAM cell), while also the EEPROM process steps add additional costs, resulting in a memory with a cost price of about 3 times the cost of standard SRAM memory.
Data logging is one area where nvSRAMs are needed. Point of sale (POS) terminals/smart terminals are now able to approve payment transactions without having to obtain approval from a remote server. Because secure data resides in the terminal, a lot of time can be saved in terms of the over the air verification which is slow as well as intrusion prone.
Motor vehicle crash boxes are another area where nvSRAMs could be employed effectively. The vehicle state data at the time of the crash can go a long way in validating the claims of any party involved in the crash and finding the reason of the crash. This has huge financial implications in the insurance industry, and the concept of having crash boxes in passenger/commercial vehicles, such as the ‘black box’ utilized in airplanes, could become a defacto standard in the near future. nvSRAMs with their fast read/write capabilities are a good fit for these applications. Similar critical applications such as medical equipment and high-end servers can use nvSRAMs to store their data. In case of an external power failure or unforeseen calamities, nvSRAM can hold the data without external intervention. Hence, nvSRAMs provide a flexibility of an EEPROM but at SRAM speeds. Applications in environments where field service is not possible/costly such as data loggers spread across geographies, routers and equipment in in-hospitable conditions can use nvSRAMs because nvSRAM do not use batteries.
Another architecture where MEMS devices may be used is NOR architecture. MEMS NOR architecture requires at least one transistor in each memory cell. Because of the NMOS device in each memory cell, area underneath the MEMS could not be utilized. For MEMS NOR architecture, The MEMS memory cells take up 50% area of MEMS memory array area for small bit count (i.e., a few Kbits) design or a lot more (e.g. 80%) for bigger memory size. Thus, MEMS NOR architecture needs further development to utilize less of the memory array area.
Analog and mixed-signal chips are another area where MEMS devices may be used. There are many analog and mixed-signals chips, which require some form of fine-tuning to achieve a proper functioning of the device within its specifications. Some examples of devices that typically require fine-tuning are: DA and AD converters, operational amplifiers, filters, digital potentiometers, etc. This fine-tuning usually requires redefining the value of one or more resistors and capacitors and occasionally even inductors. These can either be controlled in an analog manner (e.g., Varicap) or a digital manner. As true analog varicaps and analog potentiometers can't be made inside a chip, they are mimicked by a network of capacitors and resistors, which can be switched on or off within the network by means of a transistor. Switching these transistors needs to be established one or more times during calibration of the circuit, and they need to stay in the same position during the normal operation of the circuit. Even more, the circuit needs to memorize the position of these switches also when no power is supplied to the circuit. Hence, it requires some non-volatile memory to retain the position of these switches.
Today, the non-volatile elements can be either one time programmable or multiple times programmable. In the case of a one-time programmable solution, there are traditionally the following options. First, a ‘laser fuse’, which is a small wire placed on the chip, which will be melted away by means of exposure to a small laser bundle. Second, an ‘anti-fuse’, which is a high impedance via-connection between two wires on the chip which can be blown-up to become a low impedance connection. Third, an ‘electrical fuse’, which is a special wire on the chip, which can be electrically blown-up to become a high impedance. Fourth, blowing-up a transistor, which becomes a high impedance value versus a low impedance, when normally switched on. One of the issues with one-time programmable devices is that they can't be tested in both states prior to releasing it to a customer.
Some analog and mixed signal devices are programmed only once but still will use a multi-times programmable element in order to apply a decent test prior to active usage. Other analog and mixed signal devices simply are programmed more than once and therefore prefer to use a multiple time programmable element. Examples of technologies for multiple programmable elements include at least four different technologies. First among the examples is floating gate techniques. The floating gates are transistors with an extra floating gate, which can get charged by applying different high voltages. A charged floating gate will provide another behavior of such a transistor, which can be detect as a difference in current at the same gate voltage. There are different variations of this technology like: EPROM, EEPROM, flash, NOR flash, NAND flash, SONOS etc. Second among the examples is a ferro-electric technique where a ferro-electric material is used as the dielectric of a capacitor resulting in two different values for this capacitor, depending on the bias of the voltage. Third among the examples is a magnetic-resistive technique of which two different versions exist. Fourth among the examples is phase change techniques.
Another area where MEMS devices would be beneficial is field-programmable gate arrays (FPGAs). A FPGA is a semiconductor device that can be configured by the customer or designer after manufacturing—hence the name “field-programmable”. FPGAs are programmed using a logic circuit diagram or a source code in a hardware description language (HDL) to specify how the chip will work. They can be used to implement any logical function that an application-specific integrated circuit (ASIC) could perform, but the ability to update the functionality after shipping offers advantages for many applications.
FPGAs contain programmable logic components called “logic blocks”, and a hierarchy of reconfigurable interconnects that allow the blocks to be “wired together”—somewhat like a one-chip programmable breadboard. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.
It would be beneficial to be able to fabricate FPGAs, NAND, nvSRAM, AMS chips and memory logic devices utilizing less chip space without affecting front end of the line (FEOL) processes.